SPS IPC Drives 2018
Fraunhofer IPMS: TSN IP Core for real-time capable Ethernet
Time Sensitive Networking (TSN) is a standard that allows time-controlled and prioritized transmission of real-time critical messages via standard Ethernet hardware for the first time. With the TSN IP Core, developers at Fraunhofer IPMS offer system manufacturers and operators the opportunity to equip their devices for the new TSN standards.
Industry 4.0 is already a reality in many companies. In intelligent automation systems, more and more sensors, machines, control and regulation units are networked with each other. This not only means that ever larger amounts of data are being generated. The data must also flow with increasing accuracy, especially at the control and sensor/actuator level - often in real time. Numerous manufacturers of industrial end devices and switches are currently in the process of making their devices TSN-capable. This is because the Ethernet network technology widely used in industrial automation technology is not designed for hard real-time transmission due to latency times and non-deterministic delays in overload situations. Fraunhofer IPMS supports companies in this with a so-called IP core.
"Our TSN IP core helps manufacturers and operators of manufacturing and process automation systems who want to expand their network devices to meet the standards of Time Sensitive Networking," explains Dr. Frank Deicke, head of the research group at Fraunhofer IPMS. "Ethernet TSN has the advantage that data packets with real-time requirements can be prioritized over less time-critical messages and transmitted deterministically and in a time-controlled manner via standard Ethernet hardware over widely branched networks. Manufacturer-specific real-time fieldbuses, which require special hardware support, are not compliant with the IEEE 802.1 and 802.3 standards and often interfere with each other, thus become superfluous."
The TSN IP core developed by Fraunhofer IPMS includes hardware modules for time synchronization (IEEE 802.1AS) and data stream management (traffic shaping) in accordance with the IEEE 802.1Qav and 802.1Qbv standards, as well as a dedicated Ethernet MAC for low latency. The IP core uses standard AMBA or Avalon interfaces to facilitate integration into custom circuits and FPGA solutions. It is available as synthesizable source code or as a netlist.
At the trade fair, the developers from Fraunhofer IPMS will be presenting the TSN IP core together with industrial-grade solutions and customer evaluation kits for wireless optical data transmission (Li-Fi) for shorter and longer ranges.
SPS IPC Drives: Hall 7a, Stand 246









